16 #ifndef __AXIREMOVEWRITERESPONSE_H__ 17 #define __AXIREMOVEWRITERESPONSE_H__ 20 #include <nvhls_connections.h> 21 #include <nvhls_marshaller.h> 22 #include <nvhls_assert.h> 25 #include <TypeToBits.h> 53 template <
typename CfgMaster,
typename CfgSlave,
int maxInFlight>
55 static const int kDebugLevel = 6;
68 typename axiM::read::template slave<> axiM_read;
69 typename axiM::write::template slave<> axiM_write;
70 typename axiS::read::template master<> axiS_read;
71 typename axiS::write::template master<> axiS_write;
94 axiM_read(
"axiM_read"),
95 axiM_write(
"axiM_write"),
96 axiS_read(
"axiS_read"),
97 axiS_write(
"axiS_write"),
103 dummyB.in(axiS_write.b);
105 SC_THREAD(axi_read_ar);
106 sensitive << clk.pos();
109 SC_THREAD(axi_read_r);
110 sensitive << clk.pos();
113 SC_THREAD(axi_write);
114 sensitive << clk.pos();
120 axiM_read.ar.Reset();
121 axiS_read.ar.Reset();
122 #pragma hls_pipeline_init_interval 1 123 #pragma pipeline_stall_mode flush 126 if (axiM_read.ar.PopNB(AR)) {
127 axiS_read.ar.Push(BitsToType<typename axiS::AddrPayload>(
TypeToBits(AR)));
135 #pragma hls_pipeline_init_interval 1 136 #pragma pipeline_stall_mode flush 139 if (axiS_read.r.PopNB(R)) {
140 axiM_read.r.Push(BitsToType<typename axiM::ReadPayload>(
TypeToBits(R)));
146 B.resp = axiM::Enc::XRESP::OKAY;
149 axiS_write.w.Reset();
150 axiS_write.aw.Reset();
152 wresp_id_q_out.reset();
154 bool wresp_id_q_full = 0;
155 bool wresp_id_q_empty = 0;
156 bool wresp_id_q_out_full = 0;
157 bool wresp_id_q_out_empty = 0;
159 #pragma hls_pipeline_init_interval 2 160 #pragma pipeline_stall_mode flush 164 wresp_id_q_full = wresp_id_q.isFull();
165 wresp_id_q_empty = wresp_id_q.isEmpty();
166 wresp_id_q_out_full = wresp_id_q_out.isFull();
167 wresp_id_q_out_empty = wresp_id_q_out.isEmpty();
169 if (!wresp_id_q_full) {
170 if (axiM_write.aw.PopNB(AW)) {
171 axiS_write.aw.Push(BitsToType<typename axiS::AddrPayload>(
TypeToBits(AW)));
172 wresp_id_q.push(AW.id);
176 if (!wresp_id_q_empty && !wresp_id_q_out_full) {
177 if (axiM_write.w.PopNB(W)) {
178 axiS_write.w.Push(BitsToType<typename axiS::WritePayload>(
TypeToBits(W)));
179 if (W.last == 1) wresp_id_q_out.push(wresp_id_q.pop());
183 if (!wresp_id_q_out_empty) {
184 B.id = wresp_id_q_out.pop();
185 axiM_write.b.Push(B);
A simple shim that converts between two AXI configs by removing write responses.
A struct composed of the signals associated with an AXI write response.
A struct composed of the signals associated with AXI write data.
A struct composed of the signals associated with AXI read and write requests.
A struct composed of the signals associated with an AXI read response.
The base axi4 class parameterized according a valid config.
sc_lv< Wrapped< T >::width > TypeToBits(T in)
Convert Type to logic vector.
Compute Celing of log2 of a constant.
#define NVHLS_NEG_RESET_SIGNAL_IS(port)
ENABLE_SYNC_RESET define: Select synchronous or asynchronous reset.Matchlib uses asynchronous, active-low reset by default. Defining ENABLE_SYNC_RESET will use synchronous, active-low reset instead. The macros NVHLS_NEG_RESET_SIGNAL_IS() and NVHLS_POS_RESET_SIGNAL_IS() can be used in place of SystemC's reset_signal_is() and async_reset_signal_is() so that ENABLE_SYNC_RESET can select type.