MatchLib
Class Index
A | B | C | D | E | F | I | L | M | N | O | P | R | S | T | U | W | X
  A  
CombinationalBufferedPorts< Message, BufferSizeRead, 0 > (Connections)   Module (match)   
  T  
deserializer< Packet< PacketDataWidth, DestWidthPerHop, MaxHops, PacketIdWidth >, Flit< FlitDataWidth, 0, 0, PacketIdWidth, FlitId, WormHole >, 0, WormHole >   
Concat   
  N  
deserializer< Packet< PacketDataWidth, DestWidthPerHop, MaxHops, PacketIdWidth >, Flit< FlitDataWidth, 0, 0, PacketIdWidth, FlitId, WormHole >, buffersize, WormHole >   
axi4::AddrPayload (axi)   Concat< BaseTemplate, ElemW, 1 >   Tracer (match)   
  i  
Arbiter   Concat< BaseTemplate, ElemW, 2 >   nv_array::NNode (nvhls)   
  U  
Arbiter< 1, Roundrobin >   CSVFileReader   
  O  
index_width (nvhls)   
Arbiter< size_, Static >   
  D  
UIntOrEmpty (nvhls)   
  l  
ArbitratedCrossbar   OutBuffered (Connections)   UIntOrEmptywCheck (nvhls)   
ArbitratedScratchpad   DummySink (Connections)   OutNetwork (Connections)   UIntOrEmptywCheck< false, W > (nvhls)   lite (axi::cfg)   
ArbitratedScratchpadDP   DummySource (Connections)   OutNetworkCredit (Connections)   UIntOrEmptywCheck< true, W > (nvhls)   lite_nowstrb (axi::cfg)   
AXI4_Encoding::ARCACHE (axi)   
  E  
  P  
  W  
log2_ceil (nvhls)   
AXI4_Encoding::AWCACHE (axi)   log2_ceil< 0 > (nvhls)   
AXI4_Encoding::AXBURST (axi)   EmptyField (nvhls)   Packet   WHVCRouterBase   log2_floor (nvhls)   
AXI4_Encoding (axi)   
  F  
Packet< DataWidth, DestWidthPerHop, MaxHops, 0 >   WHVCSourceRouter   log2_floor< 0 > (nvhls)   
AxiAddWriteResponse   Pipeline (Connections)   axi4::WRespPayload (axi)   
  m  
AxiArbiter   FIFO   Pipeline< Message, TLM_PORT > (Connections)   axi4::WritePayload (axi)   
AxiLiteSlaveToMem   FIFO< DataType, 0, NumBanks >   PriEnc   WrRequest   axi4::read::master (axi)   
AxiMasterGate   FIFO< DataType, 1, 1 >   PriEnc< VecT, ValT, IdxT, 1 >   WrResp   axi4::write::master (axi)   
AxiRemoveWriteResponse   FIFO< DataType, 1, NumBanks >   
  R  
  X  
masterCfg   
AxiSlaveToMem   Flit   mem_array   
AxiSlaveToReadyValid   Flit< DataWidth, 0, 0, 0, FlitId, WormHole >   RdRequest   AXI4_Encoding::XRESP (axi)   mem_array_2d   
AxiSlaveToReg   Flit< DataWidth, 0, 0, PacketIdWidth, FlitId, WormHole >   RdResp   
  a  
mem_array_2d_transp   
AxiSplitter   Flit< DataWidth, DestWidthPerHop, MaxHops, PacketIdWidth, FlitId, StoreForward >   axi4::ReadPayload (axi)   mem_array_sep   
  B  
FlitId2bit   ReorderBuf   axi4 (axi)   
  n  
Flusher (match)   ReorderBufWBeats   
  b  
Buffer (Connections)   
  I  
Request   nbits (nvhls)   
Buffer< Message, NumEntries, TLM_PORT > (Connections)   
  S  
Scratchpad::bank_req_t   next_pow2 (nvhls)   
Bypass (Connections)   InBuffered (Connections)   ArbitratedScratchpad::bank_req_t   no_wresp (axi::cfg)   
Bypass< Message, TLM_PORT > (Connections)   InNetwork (Connections)   Scratchpad   ArbitratedScratchpad::bank_rsp_t   no_wstrb (axi::cfg)   
BypassBuffered (Connections)   InNetworkCredit (Connections)   Sink (Connections)   
  c  
nv_array (nvhls)   
BypassBuffered< Message, NumEntries, TLM_PORT > (Connections)   
  M  
Slave   nv_array< Type, 0 > (nvhls)   
  C  
SlaveFromFile   axi4::read::chan (axi)   nv_scvector (nvhls)   
Master   StateSignal (Connections)   axi4::write::chan (axi)   nvhls_message   
ChannelBinder (Connections)   MasterFromFile   StateSignal< Message, DIRECT_PORT > (Connections)   cli_req_t   nvhls_t (nvhls)   
CLITYPE_T   Minmax   StateSignal< Message, MARSHALL_PORT > (Connections)   cli_rsp_t   nvhls_t< N, false > (nvhls)   
CombinationalBufferedPorts (Connections)   Minmax< ArrT, ElemT, IdxT, is_max, 1 >   StateSignal< Message, SYN_PORT > (Connections)   
  d  
nvhls_t< N, true > (nvhls)   
CombinationalBufferedPorts< Message, 0, BufferSizeWrite > (Connections)   Minmax< ArrT, ElemT, IdxT, is_max, 2 >   StateSignal< Message, TLM_PORT > (Connections)   
  r  
deserializer   
axi4::read (axi)   
A | B | C | D | E | F | I | L | M | N | O | P | R | S | T | U | W | X