Class Hierarchy
This inheritance list is sorted roughly, but not completely, alphabetically:
[detail level 1234]
 CArbiter< size_, ArbiterType >A generalized implementation of generic n-way roundrobin arbiter
 CArbiter< 1, Roundrobin >Simplified specialization of a single entry arbiter to be implemented as single passthrough of valid bit. Usage identical to generic Arbiter class
 CArbiter< num_ports >
 CArbiter< NumInputs >
 CArbiter< size_, Static >Static arbitration specialization. Usage similar to generic Arbiter class
 CArbitratedCrossbar< DataType, NumInputs, NumOutputs, LenInputBuffer, LenOutputBuffer >Crossbar with conflict arbitration and input queuing
 CArbitratedCrossbar< ArbitratedScratchpad::bank_req_t, NumInputs, NumBanks, InputQueueLen, 0 >
 CArbitratedCrossbar< bankread_req_t, kNumReadPorts, kNumBanks, 0, 0 >
 CArbitratedCrossbar< bankwrite_req_t, kNumWritePorts, kNumBanks, 0, 0 >
 CArbitratedScratchpad< DataType, CapacityInBytes, NumInputs, NumBanks, InputQueueLen >Scratchpad Memories with arbitration and queuing
 CArbitratedScratchpadDP< kNumBanks, kNumReadPorts, kNumWritePorts, kEntriesPerBank, WordType, isSF, IsSPRAM >ArbitratedScratchpad with dual port support
 Caxi::AXI4_Encoding::ARCACHEHardcoded values for the ARCACHE field
 Caxi::AXI4_Encoding::AWCACHEHardcoded values for the AWCACHE field
 Caxi::AXI4_Encoding::AXBURSTHardcoded values shared by the ARBURST and AWBURST fields
 Caxi::axi4< Cfg >The base axi4 class parameterized according a valid config
 Caxi::AXI4_EncodingHardcoded values associated with the AXI4 standard
 CScratchpad< T, N, CAPACITY_IN_BYTES >::bank_req_t
 Caxi::axi4< Cfg >::read::chan< PortType >The AXI read channel, used for connecting an AXI master and AXI slave
 Caxi::axi4< Cfg >::write::chan< PortType >The AXI write channel, used for connecting an AXI master and AXI slave
 CConnections::ChannelBinder< Message, NumEntries >
 CConcat< BaseTemplate, ElemW, NumElements >
 CConcat< BaseTemplate, ElemW, 1 >
 CConcat< BaseTemplate, ElemW, 2 >
 CCSVFileReaderA helper class to read CSV files
 CFIFO< DataType, FifoLen, NumBanks >Configurable FIFO class
 CFIFO< ArbitratedScratchpad::bank_req_t, LenOutputBuffer, NumOutputs >
 CFIFO< bankread_req_t, LenOutputBuffer, NumOutputs >
 CFIFO< bankwrite_req_t, LenOutputBuffer, NumOutputs >
 CFIFO< bool, Depth >
 CFIFO< BuffIdx, buffersize >
 CFIFO< DataDest, LenInputBuffer, NumInputs >
 CFIFO< DataType, 0, NumBanks >
 CFIFO< DataType, 1, 1 >Specialization for single entry and single bank for QoR optimization
 CFIFO< DataType, 1, NumBanks >Specialization for single entry and NumBanks for QoR optimization
 CFIFO< DataType, LenOutputBuffer, NumOutputs >
 CFIFO< Flit_t, buffersize, num_ports *num_vchannels >
 CFIFO< inFlight_t, maxOutstandingRequests >
 CFIFO< Message, BufferSize >
 CFIFO< Message, BufferSizeRead >
 CFIFO< Message, BufferSizeWrite >
 CFIFO< RdRequest< Cfg >, 4 >
 CFIFO< typename axi::axi4::AddrPayload, fifoDepth >
 CFIFO< typename axi::axi4::BId, maxInFlight >
 CFIFO< typename axi::axi4::ReadPayload, fifoDepth >
 CFIFO< typename axi::axi4::WRespPayload, fifoDepth >
 CFIFO< WrRequest< Cfg >, 4 >
 CFlit< DataWidth, DestWidthPerHop, MaxHops, PacketIdWidth, FlitId, Rtype >
 Cnvhls::index_width< X >Compute index width of a constant
 Caxi::cfg::liteAn AXI configuration corresponding to the AXI4-Lite standard
 Caxi::cfg::lite_nowstrbA configuration similar to AXI4-Lite, but without write strobes
 Cnvhls::log2_ceil< X >Compute Celing of log2 of a constant
 Cnvhls::log2_ceil< 0 >Log2 of 0 is not defined: generate compiler error
 Cnvhls::log2_floor< X >Compute Floor of log2 of a constant
 Cnvhls::log2_floor< 0 >Log2 of 0 is not defined: generate compiler error
 Caxi::axi4< Cfg >::read::master< PortType >The AXI read master port. This port has an AR request channel as output and an R response channel as input
 Caxi::axi4< Cfg >::write::master< PortType >The AXI write master port. This port has AW and W request channels as outputs and a B response channel as input
 CmasterCfgAn example config for the AXI master
 Cmem_array< T, N >
 Cmem_array_2d< T, N, A >
 Cmem_array_2d_transp< T, N, A >
 Cmem_array_sep< T, NumEntries, NumBanks, NumByteEnables >Abstract Memory Class
 Cmem_array_sep< ArbitratedScratchpad::bank_req_t, FifoLen *NumBanks, NumBanks >
 Cmem_array_sep< bankread_req_t, FifoLen *NumBanks, NumBanks >
 Cmem_array_sep< bankwrite_req_t, FifoLen *NumBanks, NumBanks >
 Cmem_array_sep< bool, FifoLen *1, 1 >
 Cmem_array_sep< BuffIdx, FifoLen *1, 1 >
 Cmem_array_sep< Data, capacity_in_bytes, banks >
 Cmem_array_sep< Data, Depth, 1 >
 Cmem_array_sep< DataDest, FifoLen *NumBanks, NumBanks >
 Cmem_array_sep< DataType, CapacityInBytes, NumBanks >
 Cmem_array_sep< DataType, FifoLen *NumBanks, NumBanks >
 Cmem_array_sep< EntryNum, InFlight, 1 >
 Cmem_array_sep< Flit_t, FifoLen *NumBanks, NumBanks >
 Cmem_array_sep< inFlight_t, FifoLen *1, 1 >
 Cmem_array_sep< Message, FifoLen *1, 1 >
 Cmem_array_sep< RdRequest< Cfg >, FifoLen *1, 1 >
 Cmem_array_sep< RdResp< Cfg >, Depth, 1 >
 Cmem_array_sep< T, CAPACITY_IN_BYTES, N >
 Cmem_array_sep< typename axi::axi4::AddrPayload, FifoLen *1, 1 >
 Cmem_array_sep< typename axi::axi4::BId, FifoLen *1, 1 >
 Cmem_array_sep< typename axi::axi4::ReadPayload, FifoLen *1, 1 >
 Cmem_array_sep< typename axi::axi4::WRespPayload, FifoLen *1, 1 >
 Cmem_array_sep< WordType, kNumBanks *kEntriesPerBank, kNumBanks >
 Cmem_array_sep< WrRequest< Cfg >, FifoLen *1, 1 >
 Cmem_array_sep< WrResp< Cfg >, Depth, 1 >
 CMinmax< ArrT, ElemT, IdxT, is_max, Width >Compile-time minmax tree
 CMinmax< ArrT, ElemT, IdxT, is_max, 1 >
 CMinmax< ArrT, ElemT, IdxT, is_max, 2 >
 Cnvhls::nbits< X >Compute number of bits to represent a constant
 Cnvhls::next_pow2< n_val >Compute power of 2 value greater than a given value
 Cnvhls::nv_array< Type, VectorLength >::NNode< A, K >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_rd_master_ar, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_rd_master_r, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_rd_slave_ar, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_rd_slave_r, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_wr_master_aw, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_wr_master_b, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_wr_master_w, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_wr_slave_aw, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_wr_slave_b, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< axi_wr_slave_w, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< BankType, VectorLength-1 >
 Cnvhls::nv_array< Type, VectorLength >::NNode< Type, VectorLength-1 >
 Caxi::cfg::no_wrespAn AXI configuration with no write responses
 Caxi::cfg::no_wstrbAn AXI configuration with no write strobes
 Cnvhls::nv_array< Type, VectorLength >An implementation of array that declares VectorLength variables for array of size VectorLength
 Cnvhls::nv_array< axi_rd_master_ar, numSlaves >
 Cnvhls::nv_array< axi_rd_master_r, numSlaves >
 Cnvhls::nv_array< axi_rd_slave_ar, numMasters >
 Cnvhls::nv_array< axi_rd_slave_r, numMasters >
 Cnvhls::nv_array< axi_wr_master_aw, numSlaves >
 Cnvhls::nv_array< axi_wr_master_b, numSlaves >
 Cnvhls::nv_array< axi_wr_master_w, numSlaves >
 Cnvhls::nv_array< axi_wr_slave_aw, numMasters >
 Cnvhls::nv_array< axi_wr_slave_b, numMasters >
 Cnvhls::nv_array< axi_wr_slave_w, numMasters >
 Cnvhls::nv_array< BankType, NumBanks >
 Cnvhls::nvhls_t< N, B >Definition of vendor agnostic integer data types
 Cnvhls::nvhls_t< 1 >
 Cnvhls::nvhls_t< N, false >
 Cnvhls::nvhls_t< N, true >
 CPriEnc< VecT, ValT, IdxT, Width >
 CPriEnc< VecT, ValT, IdxT, 1 >
 Caxi::axi4< Cfg >::readThe AXI read class
 CReorderBuf< Data, Depth, InFlight >Reorder Buffer that allows out-of-order writes to queue and in-order reads
 CReorderBuf< RdResp< Cfg >, Depth, InFlight >
 CReorderBuf< WrResp< Cfg >, ROBDepth, MaxInFlightTrans >
 Cnvhls::s_N< N >
 Cnvhls::s_N< 0 >
 Cnvhls::s_N< N >::s_X< X >
 Cnvhls::s_N< 0 >::s_X< X >
 Caxi::axi4< Cfg >::read::slave< PortType >The AXI read slave port. This port has an AR request channel as input and an R response channel as output
 Caxi::axi4< Cfg >::write::slave< PortType >The AXI write slave port. This port has AW and W request channels as inputs and a B response channel as output
 Caxi::cfg::standardA standard AXI configuration
 CConnections::StateSignal< Message, port_marshall_type >
 CConnections::StateSignal< Message, DIRECT_PORT >
 CConnections::StateSignal< Message, MARSHALL_PORT >
 CConnections::StateSignal< Message, SYN_PORT >
 Cmatch::TracerTracer class to dump simulation stats to an output stream (stdout by default)
 Cnvhls::UIntOrEmpty< W >The UIntOrEmpty class is used to define a bitvector that can have a bitwidth of 0
 Cnvhls::UIntOrEmpty< ALEN_WIDTH >
 Cnvhls::UIntOrEmpty< ASIZE_WIDTH >
 Cnvhls::UIntOrEmpty< AUSER_WIDTH >
 Cnvhls::UIntOrEmpty< BID_WIDTH >
 Cnvhls::UIntOrEmpty< BURST_WIDTH >
 Cnvhls::UIntOrEmpty< BUSER_WIDTH >
 Cnvhls::UIntOrEmpty< CACHE_WIDTH >
 Cnvhls::UIntOrEmpty< ID_WIDTH >
 Cnvhls::UIntOrEmpty< LAST_WIDTH >
 Cnvhls::UIntOrEmpty< RUSER_WIDTH >
 Cnvhls::UIntOrEmpty< WSTRB_WIDTH >
 Cnvhls::UIntOrEmpty< WUSER_WIDTH >
 Cnvhls::UIntOrEmptywCheck< bool, W >A class to determine whether to instantiate an NVUINT or an EmptyField
 Cnvhls::UIntOrEmptywCheck< false, W >Template specialization to instantiate an EmptyField if the width of the UIntOrEmpty is 0
 Cnvhls::UIntOrEmptywCheck< true, W >Template specialization to instantiate an NVUINT if the width of the UIntOrEmpty is greater than 0
 Caxi::axi4< Cfg >::writeThe AXI write class
 Caxi::AXI4_Encoding::XRESPHardcoded values shared by the RRESP and BRESP fields