| ►Naxi | The axi namespace contains classes and definitions related to the AXI standard |
| ►Ncfg | Examples of valid AXI configs |
| Cstandard | A standard AXI configuration |
| Cno_wresp | An AXI configuration with no write responses |
| Cno_wstrb | An AXI configuration with no write strobes |
| Clite | An AXI configuration corresponding to the AXI4-Lite standard |
| Clite_nowstrb | A configuration similar to AXI4-Lite, but without write strobes |
| ►Caxi4 | The base axi4 class parameterized according a valid config |
| CAddrPayload | A struct composed of the signals associated with AXI read and write requests |
| ►Cread | The AXI read class |
| Cchan | The AXI read channel, used for connecting an AXI manager and AXI subordinate |
| Cmanager | The AXI read manager port. This port has an AR request channel as output and an R response channel as input |
| Csubordinate | The AXI read subordinate port. This port has an AR request channel as input and an R response channel as output |
| CReadPayload | A struct composed of the signals associated with an AXI read response |
| CWRespPayload | A struct composed of the signals associated with an AXI write response |
| ►Cwrite | The AXI write class |
| Cchan | The AXI write channel, used for connecting an AXI manager and AXI subordinate |
| Cmanager | The AXI write manager port. This port has AW and W request channels as outputs and a B response channel as input |
| Csubordinate | The AXI write subordinate port. This port has AW and W request channels as inputs and a B response channel as output |
| CWritePayload | A struct composed of the signals associated with AXI write data |
| ►CAXI4_Encoding | Hardcoded values associated with the AXI4 standard |
| CARCACHE | Hardcoded values for the ARCACHE field |
| CAWCACHE | Hardcoded values for the AWCACHE field |
| CAXBURST | Hardcoded values shared by the ARBURST and AWBURST fields |
| CXRESP | Hardcoded values shared by the RRESP and BRESP fields |
| ►NConnections | |
| CCombinationalBufferedPorts | |
| CCombinationalBufferedPorts< Message, BufferSizeRead, 0 > | |
| CCombinationalBufferedPorts< Message, 0, BufferSizeWrite > | |
| CInBuffered | |
| COutBuffered | |
| CStateSignal | |
| CStateSignal< Message, SYN_PORT > | |
| CStateSignal< Message, MARSHALL_PORT > | |
| CStateSignal< Message, DIRECT_PORT > | |
| CStateSignal< Message, TLM_PORT > | |
| CBypass | |
| CBypass< Message, TLM_PORT > | |
| CPipeline | |
| CPipeline< Message, TLM_PORT > | |
| CBypassBuffered | |
| CBypassBuffered< Message, NumEntries, TLM_PORT > | |
| CBuffer | |
| CBuffer< Message, NumEntries, TLM_PORT > | |
| CSink | |
| CDummySink | |
| CDummySource | |
| CChannelBinder | |
| CInNetwork | |
| COutNetwork | |
| CInNetworkCredit | |
| COutNetworkCredit | |
| ►Nmatch | |
| CModule | Matchlib Module class: a wrapper of sc_module with tracing and stats support |
| CFlusher | |
| CTracer | Tracer class to dump simulation stats to an output stream (stdout by default) |
| ►Nnvhls | |
| Cnv_array_pow2 | |
| Cnv_array_pow2< 1 > | |
| Cnv_array_bank_array_no_assert_base | |
| Cnv_array_bank_array_no_assert_base< B, 1 > | |
| Cnv_array | An implementation of array that declares VectorLength variables for array of size VectorLength |
| ►Cs_N | |
| Cs_X | |
| ►Cs_N< 0 > | |
| Cs_X | |
| Cnbits | Compute number of bits to represent a constant |
| Clog2_floor | Compute Floor of log2 of a constant |
| Clog2_floor< 0 > | Log2 of 0 is not defined: generate compiler error |
| Clog2_ceil | Compute Celing of log2 of a constant |
| Clog2_ceil< 0 > | Log2 of 0 is not defined: generate compiler error |
| Cnext_pow2 | Compute power of 2 value greater than a given value |
| Cindex_width | Compute index width of a constant |
| Cnvhls_t | Definition of vendor agnostic integer data types |
| Cnvhls_t< N, true > | |
| Cnvhls_t< N, false > | |
| Cnv_scvector | Vector helper container with vector operations |
| CEmptyField | Used for rudimentary support for members of a struct that can be configured to have zero width |
| CUIntOrEmptywCheck | A class to determine whether to instantiate an NVUINT or an EmptyField |
| CUIntOrEmptywCheck< true, W > | Template specialization to instantiate an NVUINT if the width of the UIntOrEmpty is greater than 0 |
| CUIntOrEmptywCheck< false, W > | Template specialization to instantiate an EmptyField if the width of the UIntOrEmpty is 0 |
| CUIntOrEmpty | The UIntOrEmpty class is used to define a bitvector that can have a bitwidth of 0 |
| CArbiter | A generalized implementation of generic n-way roundrobin arbiter |
| CArbiter< 1, Roundrobin > | Simplified specialization of a single entry arbiter to be implemented as single passthrough of valid bit. Usage identical to generic Arbiter class |
| CArbiter< size_, Static > | Static arbitration specialization. Usage similar to generic Arbiter class |
| CArbitratedCrossbar | Crossbar with conflict arbitration and input queuing |
| ►CArbitratedScratchpad | Scratchpad Memories with arbitration and queuing |
| Cbank_req_t | |
| Cbank_rsp_t | |
| CArbitratedScratchpadDP | ArbitratedScratchpad with dual port support |
| CAxiAddWriteResponse | A simple shim that converts between two AXI configs by adding write responses |
| CAxiArbiter | An n-way arbiter that connects multiple AXI manager ports to a single AXI subordinate port |
| CAxiLiteSubordinateToMem | An AXI subordinate SRAM for the AXI-Lite protocol |
| CAxiManagerGate | An AXI manager that converts from a simple request/response interface to AXI with reordering support |
| CAxiRemoveWriteResponse | A simple shim that converts between two AXI configs by removing write responses |
| CAxiSplitter | An n-way splitter that connects a single AXI manager port to a multiple AXI subordinate ports |
| CAxiSubordinateToCSReg | An AXI subordinate containing memory-mapped registers |
| CAxiSubordinateToMem | An AXI subordinate SRAM |
| CAxiSubordinateToReadyValid | An AXI subordinate that converts AXI requests into a simplified format |
| CAxiSubordinateToReg | An AXI subordinate containing memory-mapped registers |
| Ccli_req_t | |
| Ccli_rsp_t | |
| CCLITYPE_T | |
| CConcat | |
| CConcat< BaseTemplate, ElemW, 1 > | |
| CConcat< BaseTemplate, ElemW, 2 > | |
| CCSVFileReader | A helper class to read CSV files |
| Cdeserializer | Deserializer for store-forward router |
| Cdeserializer< Packet< PacketDataWidth, DestWidthPerHop, MaxHops, PacketIdWidth >, Flit< FlitDataWidth, 0, 0, PacketIdWidth, FlitId, WormHole >, 0, WormHole > | Deserializer for Wormhole router without input buffer |
| Cdeserializer< Packet< PacketDataWidth, DestWidthPerHop, MaxHops, PacketIdWidth >, Flit< FlitDataWidth, 0, 0, PacketIdWidth, FlitId, WormHole >, buffersize, WormHole > | Deserializer for Wormhole router |
| CFIFO | Configurable FIFO class |
| CFIFO< DataType, 0, NumBanks > | |
| CFIFO< DataType, 1, 1 > | Specialization for single entry and single bank for QoR optimization |
| CFIFO< DataType, 1, NumBanks > | Specialization for single entry and NumBanks for QoR optimization |
| CFlit | |
| CFlit< DataWidth, 0, 0, 0, FlitId, WormHole > | |
| CFlit< DataWidth, 0, 0, PacketIdWidth, FlitId, WormHole > | |
| CFlit< DataWidth, DestWidthPerHop, MaxHops, PacketIdWidth, FlitId, StoreForward > | Parameterized implementation of a network flit |
| CFlitId2bit | Encoding for FlitID |
| CManager | An AXI manager that generates random traffic for use in a testbench |
| CmanagerCfg | An example config for the AXI manager |
| CManagerFromFile | |
| Cmem_array | |
| Cmem_array_2d | |
| Cmem_array_2d_transp | |
| Cmem_array_opt | Abstract Memory Class |
| Cmem_array_sep | Abstract Memory Class |
| CMinmax | Compile-time minmax tree |
| CMinmax< ArrT, ElemT, IdxT, is_max, 1 > | |
| CMinmax< ArrT, ElemT, IdxT, is_max, 2 > | |
| Cnvhls_message | |
| CPacket | Parameterized implementation of a network packet |
| CPacket< DataWidth, DestWidthPerHop, MaxHops, 0 > | |
| CPriEnc | |
| CPriEnc< VecT, ValT, IdxT, 1 > | |
| CRdRequest | The struct for read requests for AxiManagerGate |
| CRdResp | The struct for read responses for AxiManagerGate |
| CReorderBuf | Reorder Buffer that allows out-of-order writes to queue and in-order reads |
| CReorderBufWBeats | An extension of ReorderBuf that allows one entry to contain multiple beats of data |
| CRequest | The base type for read or write requests for AxiManagerGate, containing common fields |
| Csc_in_conditional | An AXI manager that generates traffic according to a file for use in testbenches |
| Csc_in_conditional< T, 1 > | |
| ►CScratchpad | Parameterized banked scratchpad memory implemented as a SystemC module |
| Cbank_req_t | |
| ►CScratchpadClass | Parameterized banked scratchpad memory implemented as a C++ class (i.e. not a SystemC module) |
| Cbank_req_t | |
| ►CScratchpadTraits | Traits class for Scratchpad and ScratchpadClass |
| Cscratchpad_req_t | |
| Cserializer | Serializer for store-forward router |
| Cserializer< Packet< PacketDataWidth, DestWidthPerHop, MaxHops, 0 >, Flit< FlitDataWidth, 0, 0, 0, FlitId, WormHole >, WormHole > | Serializer for WormHole router without packet-id in flits |
| Cserializer< Packet< PacketDataWidth, DestWidthPerHop, MaxHops, PacketIdWidth >, Flit< FlitDataWidth, 0, 0, PacketIdWidth, FlitId, WormHole >, WormHole > | Serializer for WormHole router |
| CSubordinate | An AXI subordinate for use in a testbench |
| CSubordinateFromFile | An AXI subordinate with its memory prepopulated from a file for use in testbenches |
| CWHVCRouterBase | |
| CWHVCSourceRouter | Wormhole Router with virtual channels |
| CWrRequest | The struct for write requests for AxiManagerGate |
| CWrResp | The struct for write responses for AxiManagerGate |
