Timed units - implemented as sc_module

Modules
	<br>
	Wormhole router with virtual channels.
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	N-bit packets to/from M cycles of (N/M)-bit packets.
	Cache
	Direct-mapped Cache design.
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	Banked Memory Array with Crossbar.
	FlitMplex
	Mux multiple input channels to single output channel.
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	DeMux single input channel to one of multiple output channels.
	<br>
	Manager/Subordinate Interfaces & bridges for AXI interconnect.

Detailed Description