MatchLib
Modules
Timed units - implemented as sc_module

Modules

 WHVCRouter
 Wormhole router with virtual channels.
 
 SerDes
 N-bit packets to/from M cycles of (N/M)-bit packets.
 
 Cache
 Direct-mapped Cache design.
 
 Scratchpad
 Banked Memory Array with Crossbar.
 
 FlitMplex
 Mux multiple input channels to single output channel.
 
 FlitDeMplex
 DeMux single input channel to one of multiple output channels.
 
 AXI
 Master/Slave Interfaces & bridges for AXI interconnect.
 

Detailed Description