AXI

Master/Slave Interfaces & bridges for AXI interconnect. More...

Namespaces
	axi
	The axi namespace contains classes and definitions related to the AXI standard.
	axi::cfg
	Examples of valid AXI configs.

Classes
class	axi::axi4< Cfg >
	The base axi4 class parameterized according a valid config. More...
class	axi::AXI4_Encoding
	Hardcoded values associated with the AXI4 standard. More...
class	AxiAddWriteResponse< CfgMaster, CfgSlave >
	A simple shim that converts between two AXI configs by adding write responses. More...
class	AxiArbiter< axiCfg, numMasters, maxOutstandingRequests >
	An n-way arbiter that connects multiple AXI master ports to a single AXI slave port. More...
class	AxiLiteSlaveToMem< capacity >
	An AXI slave SRAM for the AXI-Lite protocol. More...
class	AxiMasterGate< Cfg, ROBDepth, MaxInFlightTrans >
	An AXI master that converts from a simple request/response interface to AXI with reordering support. More...
class	AxiRemoveWriteResponse< CfgMaster, CfgSlave, maxInFlight >
	A simple shim that converts between two AXI configs by removing write responses. More...
class	AxiSlaveToMem< axiCfg, capacity, fifoDepth >
	An AXI slave SRAM. More...
class	AxiSlaveToReadyValid< axiCfg, rvCfg >
	An AXI slave that converts AXI requests into a simplified format. More...
class	AxiSlaveToReg< axiCfg, numReg, numAddrBitsToInspect >
	An AXI slave containing memory-mapped registers. More...
class	AxiSplitter< axiCfg, numSlaves, numAddrBitsToInspect, default_output, translate_addr >
	An n-way splitter that connects a single AXI master port to a multiple AXI slave ports. More...
class	Master< axiCfg, cfg >
	An AXI master that generates random traffic for use in a testbench. More...
class	sc_in_conditional< T, enable >
	An AXI master that generates traffic according to a file for use in testbenches. More...
class	Slave< axiCfg >
	An AXI slave for use in a testbench. More...
class	SlaveFromFile< axiCfg >
	An AXI slave with its memory prepopulated from a file for use in testbenches. More...

Functions
template<typename Cfg >
	SC_MODULE (Host)
	A testbench component to verify AxiMasterGate. More...
template<typename rvCfg >
	SC_MODULE (RVSink)
	A testbench component to verify AxiSlaveToReadyValid. More...

Detailed Description

Master/Slave Interfaces & bridges for AXI interconnect.

Function Documentation

template<typename Cfg >

SC_MODULE

(

Host

)

A testbench component to verify AxiMasterGate.

Template Parameters

Cfg	A valid AXI config.

Overview

This component connects to the request-response (non-AXI) interface of AXIMasterGate. It launches read and write requests and checks for appropriate responses.

Definition at line 41 of file Host.h.

template<typename rvCfg >

SC_MODULE

(

RVSink

)

A testbench component to verify AxiSlaveToReadyValid.

Template Parameters

rvCfg

A config for the ready-valid interface that is the output of AxiSlaveToReadyValid.

Overview

This component connects to the ready-valid (non-AXI) interface of AxiSlaveToReadyValid. It contains internal state and responds to read and write requests appropriately.

The struct containing fields for the read and write request interface.

The struct containing the data field for the read response interface.

Definition at line 42 of file RVSink.h.