Polar5GEncoder#

class sionna.phy.fec.polar.Polar5GEncoder(k: int, n: int, channel_type: str = 'uplink', verbose: bool = False, *, precision: str | None = None, device: str | None = None, **kwargs)[source]#

Bases: sionna.phy.fec.polar.encoding.PolarEncoder

5G compliant Polar encoder including rate-matching following [3GPPTS38212] for the uplink scenario (UCI) and downlink scenario (DCI).

This block performs polar encoding for k information bits and rate-matching such that the codeword length is n. This includes the CRC concatenation and the interleaving as defined in [3GPPTS38212].

Note: block segmentation is currently not supported (I_seq=False).

We follow the basic structure from Fig. 6 in [Bioglio_Design].

For further details, we refer to [3GPPTS38212], [Bioglio_Design] and [Hui_ChannelCoding].

Parameters:

k (int) – Defining the number of information bits per codeword.
n (int) – Defining the codeword length.
channel_type (str) – Can be 'uplink' or 'downlink'.
verbose (bool) – If True, rate-matching parameters will be printed.
precision (str | None) – Precision used for internal calculations and outputs. If None, precision is used.
device (str | None) – Device for computation (e.g., ‘cpu’, ‘cuda:0’). If None, device is used.

Inputs:

bits – […, k], torch.float. Binary tensor containing the information bits to be encoded.

Outputs:

cw – […, n], torch.float. Binary tensor containing the codeword bits.

Notes

The encoder supports the uplink Polar coding (UCI) scheme from [3GPPTS38212] and the downlink Polar coding (DCI) [3GPPTS38212], respectively.

For 12 <= k <= 19 the 3 additional parity bits as defined in [3GPPTS38212] are not implemented as it would also require a modified decoding procedure to materialize the potential gains.

Code segmentation is currently not supported and, thus, n is limited to a maximum length of 1088 codeword bits.

For the downlink scenario, the input length is limited to k <= 140 information bits due to the limited input bit interleaver size [3GPPTS38212].

For simplicity, the implementation does not exactly re-implement the DCI scheme from [3GPPTS38212]. This implementation neglects the all-one initialization of the CRC shift register and the scrambling of the CRC parity bits with the RNTI.

Examples

import torch
from sionna.phy.fec.polar import Polar5GEncoder

k, n = 100, 200
encoder = Polar5GEncoder(k, n)

bits = torch.randint(0, 2, (10, k), dtype=torch.float32)
codewords = encoder(bits)
print(codewords.shape)
# torch.Size([10, 200])

Attributes

property enc_crc: sionna.phy.fec.crc.CRCEncoder#: CRC encoder block used for CRC concatenation.

property k_target: int#: Number of information bits including rate-matching.

property n_target: int#: Codeword length including rate-matching.

property k_polar: int#: Number of information bits of the underlying Polar code.

property n_polar: int#: Codeword length of the underlying Polar code.

property k: int#: Number of information bits including rate-matching.

property n: int#: Codeword length including rate-matching.

Methods

subblock_interleaving(u: numpy.ndarray) → numpy.ndarray[source]#

Input bit interleaving as defined in Sec 5.4.1.1 [3GPPTS38212].

Parameters:: u (numpy.ndarray) – 1D array to be interleaved. Length of u must be a multiple of 32.
Outputs:: y – Interleaved version of u with same shape and dtype as u.

channel_interleaver(c: numpy.ndarray) → numpy.ndarray[source]#

Triangular interleaver following Sec. 5.4.1.3 in [3GPPTS38212].

Parameters:: c (numpy.ndarray) – 1D array to be interleaved.
Outputs:: c_int – Interleaved version of c with same shape and dtype as c.

input_interleaver(c: numpy.ndarray) → numpy.ndarray[source]#

Input interleaver following Sec. 5.4.1.1 in [3GPPTS38212].

Parameters:: c (numpy.ndarray) – 1D array to be interleaved.
Outputs:: c_apo – Interleaved version of c with same shape and dtype as c.

build(input_shape: Tuple[int, ...]) → None[source]#

Build and check if k and input_shape match.

Parameters:: input_shape (Tuple[int, ...])

Polar5GEncoder#

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