23 #include <mem_array.h>
25 #include <axi/AxiSubordinateToReadyValid.h>
41 template <
typename rvCfg>
45 sc_in<bool> reset_bar;
47 typedef NVUINTW(rvCfg::dataWidth) Data;
48 typedef NVUINTW(rvCfg::addrWidth) Addr;
49 typedef NVUINTW(rvCfg::wstrbWidth) Wstrb;
62 static const unsigned int width =
63 rvCfg::dataWidth + rvCfg::addrWidth + rvCfg::wstrbWidth + 1;
65 template <
unsigned int Size>
66 void Marshall(Marshaller<Size>& m) {
81 static const unsigned int width = rvCfg::dataWidth;
83 template <
unsigned int Size>
84 void Marshall(Marshaller<Size>& m) {
89 static const int kDebugLevel = 4;
91 Connections::Out<Read> rv_read;
92 Connections::In<Write> rv_write;
94 std::map<Addr,
NVUINTW(8)> localMem;
96 SC_HAS_PROCESS(RVSink);
98 RVSink(sc_module_name name_)
101 reset_bar(
"reset_bar"),
103 rv_write(
"rv_write") {
105 sensitive << clk.pos();
106 async_reset_signal_is(reset_bar,
false);
118 if (rv_write.PopNB(rv_req_reg)) {
119 CDCOUT(sc_time_stamp() <<
" " << name() <<
" RV request received:"
120 <<
" data=" << hex << rv_req_reg.data
121 <<
" addr=" << hex << rv_req_reg.addr.to_uint64()
123 << rv_req_reg.wstrb.to_uint64()
124 <<
" isWrite=" << rv_req_reg.rw << endl,
127 for (
int i = 0; i < rvCfg::wstrbWidth; i++) {
128 if (rv_req_reg.wstrb[i] == 1) {
129 localMem[rv_req_reg.addr + i] =
130 nvhls::get_slc<8>(rv_req_reg.data, 8 * i);
134 for (
int i = 0; i < rvCfg::wstrbWidth; i++) {
136 rv_resp_reg.data, localMem[rv_req_reg.addr + i], 8 * i);
138 rv_read.Push(rv_resp_reg);
139 CDCOUT(sc_time_stamp() <<
" " << name() <<
" Sending RV read response"
141 << rv_resp_reg.data << endl,
SC_MODULE(RVSink)
A testbench component to verify AxiSubordinateToReadyValid.
NVUINTW(Wrapped< T >::width) TypeToNVUINT(T in)
Convert Type to NVUINT.
type1 set_slc(type1 X, type2 Y, const unsigned int i)
Function that replaces slice of bits.