104 static const int ADDR_WIDTH =
nvhls::nbits<CAPACITY_IN_WORDS - 1>::val;
107 static const int NBANKS_LOG2 =
nvhls::nbits<N - 1>::val;
110 typedef NVUINTW(NBANKS_LOG2) bank_sel_t;
111 typedef NVUINTW(ADDR_WIDTH - NBANKS_LOG2) bank_addr_t;
122 bool input_reqs_valid[N];
124 bool bank_reqs_valid[N];
126 bool bank_rsps_valid[N];
127 bool load_rsps_valid[N];
129 bank_sel_t bank_src_lane[N];
130 bank_sel_t bank_dst_lane[N];
132 void store(
req_t req) {
135 load_store(req, load_rsp);
138 rsp_t load(req_t req) {
141 load_store(req, load_rsp);
145 void load_store(req_t curr_cli_req, rsp_t& load_rsp) {
148 is_load = (curr_cli_req.opcode == LOAD);
151 #pragma hls_unroll yes
152 for (
int i = 0; i < N; i++) {
157 bank_src_lane[bank_sel] = i;
160 bank_dst_lane[i] = bank_sel;
163 for (
int j=0; j < i; j++) {
164 if (bank_dst_lane[j] == bank_sel) {
165 std::cout <<
"Conflicting bank requests indexes are: "
166 << std::dec << i <<
" " << j <<
"\n";
168 NVHLS_ASSERT_MSG(bank_dst_lane[j] != bank_sel,
"conflicting bank requests");
173 input_reqs_valid[i] = (curr_cli_req.valids[i] ==
true);
175 curr_cli_req.addr[i], NBANKS_LOG2);
177 input_reqs[i].wdata = curr_cli_req.data[i];
181 crossbar<bank_req_t, N, N>(input_reqs, input_reqs_valid, bank_src_lane,
182 bank_reqs, bank_reqs_valid);
185 #pragma hls_unroll yes
186 for (
int i = 0; i < N; i++) {
187 if ((bank_reqs_valid[i] ==
true) && is_load) {
188 bank_rsps_valid[i] =
true;
189 bank_rsps_data[i] = banks.read(bank_reqs[i].addr, i);
190 }
else if ((bank_reqs_valid[i] ==
true) && !is_load) {
191 banks.write(bank_reqs[i].addr, i, bank_reqs[i].wdata);
192 bank_rsps_valid[i] =
false;
194 bank_rsps_valid[i] =
false;
199 crossbar<T, N, N>(bank_rsps_data, bank_rsps_valid, bank_dst_lane,
200 load_rsp.data, load_rsps_valid);
201 #pragma hls_unroll yes
202 for (
int i = 0; i < N; i++) {
203 load_rsp.valids[i] = load_rsps_valid[i];
261 static const int ADDR_WIDTH =
nvhls::nbits<CAPACITY_IN_WORDS - 1>::val;
264 Connections::In<cli_req_t<T, ADDR_WIDTH, N> > cli_req;
265 Connections::Out<cli_rsp_t<T, N> > cli_rsp;
269 static const int NBANKS_LOG2 =
nvhls::nbits<N - 1>::val;
272 typedef NVUINTW(NBANKS_LOG2) bank_sel_t;
273 typedef NVUINTW(ADDR_WIDTH - NBANKS_LOG2) bank_addr_t;
287 Scratchpad(sc_module_name name_) : sc_module(name_) {
289 sensitive << clk.pos();
302 #pragma hls_pipeline_init_interval 1
303 #pragma pipeline_stall_mode flush
316 curr_cli_req = cli_req.Pop();
318 scratchpad_class.load_store(curr_cli_req, load_rsp);
319 is_load = (curr_cli_req.opcode == LOAD);
323 cli_rsp.Push(load_rsp);