Components

Here is a list of all modules:

[detail level 123]

▼Stateless datapath blocks - implemented as functions
Nvhls_int	Integer library with built-in support for sc_int and ac_int datatypes
<br>	Configurable nxn crossbar datapath
<br>	One-hot to binary convertor
▼Loosly-timed units with state - implemented as classes
<br>	Configurable n inputs arbiter
<br>	Abstract Memory Class
<br>	Configurable FIFO class
<br>	Vector helper container with vector operations
<br>	Modular IO supporting latency-insensitive channels
ArbitratedCrossbar	Crossbar with conflict arbitration and queuing
ArbitratedScratchpad	Scratchpad memories with arbitration and queuing
ReorderBuffer	Out-of-order writes into queue, in-order reads
▼Timed units - implemented as sc_module
<br>	Wormhole router with virtual channels
<br>	N-bit packets to/from M cycles of (N/M)-bit packets
Cache	Direct-mapped Cache design
<br>	Banked Memory Array with Crossbar
FlitMplex	Mux multiple input channels to single output channel
<br>	DeMux single input channel to one of multiple output channels
<br>	Manager/Subordinate Interfaces & bridges for AXI interconnect
▼Misc utilities and auxiliary constructs
<br>	Convert any datatype to bit-vector
<br>	Configurable packet and flit classes
Comptrees	Compile-time minmax tree
<br>	Debug print statements
<br>	A variant of synthesizable array implementation
<br>	Macros for synthesizable and non-synthesizable assertions
<br>	Marshaller is used to automatically convert types to logic vector and vice versa
StaticMax	StaticMax Class: returns the larger value between two unsigned integers
BitUnion2	BitUnion2 class: A union class to hold two Marshallers
<br>	Matchlib Module class: a wrapper of sc_module with tracing and stats support
<br>	Tracer class to dump simulation stats to an output stream
NVHLSVerify	Verification co-simulation support
▼Non-synthesizable components suitable for testbench construction
Pacer	Random stall generator
Set_random_seed	Set random seed
Gen_random_payload	Generate Random payload of any type